Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml- Extension
.yaml- Size
- 3653 bytes
- Lines
- 133
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DesignWare based PCIe RC/EP controller on Rockchip SoCs
maintainers:
- Shawn Lin <shawn.lin@rock-chips.com>
- Simon Xue <xxm@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
description: |+
Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip
SoCs.
properties:
clocks:
minItems: 5
items:
- description: AHB clock for PCIe master
- description: AHB clock for PCIe slave
- description: AHB clock for PCIe dbi
- description: APB clock for PCIe
- description: Auxiliary clock for PCIe
- description: PIPE clock
- description: Reference clock for PCIe
clock-names:
minItems: 5
items:
- const: aclk_mst
- const: aclk_slv
- const: aclk_dbi
- const: pclk
- const: aux
- const: pipe
- const: ref
interrupts:
minItems: 5
items:
- description:
Combined system interrupt, which is used to signal the following
interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
- description:
Combined PM interrupt, which is used to signal the following
interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
linkst_out_l0s, pm_dstate_update
- description:
Combined message interrupt, which is used to signal the following
interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
- description:
Combined legacy interrupt, which is used to signal the following
interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc,
tx_intd
- description:
Combined error interrupt, which is used to signal the following
interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
nf_err_rx, f_err_rx, radm_qoverflow
- description:
If the matching interrupt name is "msi", then this is the combined
MSI line interrupt, which is to support MSI interrupts output to GIC
controller via GIC SPI interrupt instead of GIC ITS interrupt.
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.