Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
Extension
.yaml
Size
10509 bytes
Lines
274
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DWC PCIe RP/EP controller

maintainers:
  - Jingoo Han <jingoohan1@gmail.com>
  - Gustavo Pimentel <gustavo.pimentel@synopsys.com>

description:
  Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
  properties.

select: false

properties:
  reg:
    description:
      DWC PCIe CSR space is normally accessed over the dedicated Data Bus
      Interface - DBI. In accordance with the reference manual the register
      configuration space belongs to the Configuration-Dependent Module (CDM)
      and is split up into several sub-parts Standard PCIe configuration
      space, Port Logic Registers (PL), Shadow Config-space Registers,
      iATU/eDMA registers. The particular sub-space is selected by the
      CDM/ELBI (dbi_cs) and CS2 (dbi_cs2) signals (selector bits). Such
      configuration provides a flexible interface for the system engineers to
      either map the particular space at a desired MMIO address or just leave
      them in a contiguous memory space if pure Native or AXI Bridge DBI access
      is selected. Note the PCIe CFG-space, PL and Shadow registers are
      specific for each activated function, while the rest of the sub-spaces
      are common for all of them (if there are more than one).
    minItems: 2
    maxItems: 7

  reg-names:
    minItems: 2
    maxItems: 7

  interrupts:
    description:
      There are two main sub-blocks which are normally capable of
      generating interrupts. It's System Information Interface and MSI
      interface. While the former one has some common for the Host and
      Endpoint controllers IRQ-signals, the later interface is obviously
      Root Complex specific since it's responsible for the incoming MSI
      messages signalling. The System Information IRQ signals are mainly
      responsible for reporting the generic PCIe hierarchy and Root
      Complex events like VPD IO request, general AER, PME, Hot-plug, link
      bandwidth change, link equalization request, INTx asserted/deasserted
      Message detection, embedded DMA Tx/Rx/Error.
    minItems: 1
    maxItems: 26

  interrupt-names:
    minItems: 1
    maxItems: 26

  clocks:
    description:
      DWC PCIe reference manual explicitly defines a set of the clocks required
      to get the controller working correctly. In general all of them can
      be divided into two groups':' application and core clocks. Note the
      platforms may have some of the clock sources unspecified in case if the
      corresponding domains are fed up from a common clock source.
    minItems: 1
    maxItems: 7

Annotation

Implementation Notes