Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
Extension
.yaml
Size
7822 bytes
Lines
204
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DesignWare PCIe endpoint interface

maintainers:
  - Jingoo Han <jingoohan1@gmail.com>
  - Gustavo Pimentel <gustavo.pimentel@synopsys.com>

description: |
  Synopsys DesignWare PCIe host controller endpoint

# Please create a separate DT-schema for your DWC PCIe Endpoint controller
# and make sure it's assigned with the vendor-specific compatible string.
select:
  properties:
    compatible:
      const: snps,dw-pcie-ep
  required:
    - compatible

allOf:
  - $ref: /schemas/pci/pci-ep.yaml#
  - $ref: /schemas/pci/snps,dw-pcie-common.yaml#

properties:
  reg:
    description:
      DBI, DBI2 reg-spaces and outbound memory window are required for the
      normal controller functioning. iATU memory IO region is also required
      if the space is unrolled (IP-core version >= 4.80a).
    minItems: 2
    maxItems: 7

  reg-names:
    minItems: 2
    maxItems: 7
    items:
      oneOf:
        - description:
            Basic DWC PCIe controller configuration-space accessible over
            the DBI interface. This memory space is either activated with
            CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
            with all spaces. Note iATU/eDMA CSRs are indirectly accessible
            via the PL viewports on the DWC PCIe controllers older than
            v4.80a.
          const: dbi
        - description:
            Shadow DWC PCIe config-space registers. This space is selected
            by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
            the PCI-SIG PCIe CFG-space with the shadow registers for some
            PCI Header space, PCI Standard and Extended Structures. It's
            mainly relevant for the end-point controller configuration,
            but still there are some shadow registers available for the
            Root Port mode too.
          const: dbi2
        - description:
            External Local Bus registers. It's an application-dependent
            registers normally defined by the platform engineers. The space
            can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
            be accessed over some platform-specific means (for instance
            as a part of a system controller).
          enum: [ elbi, app ]
        - description:
            iATU/eDMA registers common for all device functions. It's an
            unrolled memory space with the internal Address Translation
            Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1

Annotation

Implementation Notes