Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml

File Facts

System: Linux kernel
Corpus path: Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
Extension: .yaml
Size: 3223 bytes
Lines: 144
Domain: Support Tooling And Documentation
Bucket: Documentation
Inferred role: Support Tooling And Documentation: configuration, schema, or hardware description
Status: atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

dt-bindings/soc/ti,sci_pm_domain.h

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: TI J721E PCI EP (PCIe Wrapper)

maintainers:
  - Kishon Vijay Abraham I <kishon@ti.com>

properties:
  compatible:
    oneOf:
      - const: ti,j721e-pcie-ep
      - const: ti,j784s4-pcie-ep
      - description: PCIe EP controller in AM64
        items:
          - const: ti,am64-pcie-ep
          - const: ti,j721e-pcie-ep
      - description: PCIe EP controller in J7200
        items:
          - const: ti,j7200-pcie-ep
          - const: ti,j721e-pcie-ep

  reg:
    maxItems: 4

  reg-names:
    items:
      - const: intd_cfg
      - const: user_cfg
      - const: reg
      - const: mem

  ti,syscon-pcie-ctrl:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: Phandle to the SYSCON entry
          - description: pcie_ctrl register offset within SYSCON
    description: Specifier for configuring PCIe mode and link speed.

  power-domains:
    maxItems: 1

  clocks:
    maxItems: 1
    description: clock-specifier to represent input to the PCIe

  clock-names:
    items:
      - const: fck

  dma-coherent:
    description: Indicates that the PCIe IP block can ensure the coherency

  interrupts:
    maxItems: 1

  interrupt-names:
    items:
      - const: link_state

allOf:
  - $ref: cdns-pcie-ep.yaml#
  - if:
      properties:
        compatible:

Annotation

Immediate include surface: `dt-bindings/soc/ti,sci_pm_domain.h`.
Atlas domain: Support Tooling And Documentation / Documentation.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.