Documentation/devicetree/bindings/pci/ti-pci.txt
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/ti-pci.txt
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/pci/ti-pci.txt- Extension
.txt- Size
- 4088 bytes
- Lines
- 103
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: documentation
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
TI PCI Controllers
PCIe DesignWare Controller
- compatible: Should be "ti,dra7-pcie" for RC (deprecated)
Should be "ti,dra7-pcie-ep" for EP (deprecated)
Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
Should be "ti,dra726-pcie-rc" for dra72x in RC mode
Should be "ti,dra726-pcie-ep" for dra72x in EP mode
- phys : list of PHY specifiers (used by generic PHY framework)
- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
number of PHYs as specified in *phys* property.
- ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
where <X> is the instance number of the pcie from the HW spec.
- num-lanes as specified in ../snps,dw-pcie.yaml
- ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
module and the register offset to specify lane
selection.
HOST MODE
=========
- reg : Two register ranges as listed in the reg-names property
- reg-names : The first entry must be "ti-conf" for the TI-specific registers
The second entry must be "rc-dbics" for the DesignWare PCIe
registers
The third entry must be "config" for the PCIe configuration space
- interrupts : Two interrupt entries must be specified. The first one is for
main interrupt line and the second for MSI interrupt line.
- #address-cells,
#size-cells,
#interrupt-cells,
device_type,
ranges,
interrupt-map-mask,
interrupt-map : as specified in ../snps,dw-pcie.yaml
- ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
should contain the register offset within syscon
and the 2nd argument should contain the bit field
for setting the bit to enable unaligned
access.
DEVICE MODE
===========
- reg : Four register ranges as listed in the reg-names property
- reg-names : "ti-conf" for the TI-specific registers
"ep_dbics" for the standard configuration registers as
they are locally accessed within the DIF CS space
"ep_dbics2" for the standard configuration registers as
they are locally accessed within the DIF CS2 space
"addr_space" used to map remote RC address space
- interrupts : one interrupt entries must be specified for main interrupt.
- num-ib-windows : number of inbound address translation windows
- num-ob-windows : number of outbound address translation windows
- ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
should contain the register offset within syscon
and the 2nd argument should contain the bit field
for setting the bit to enable unaligned
access.
Optional Property:
- gpios : Should be added if a GPIO line is required to drive PERST# line
NOTE: Two DT nodes may be added for each PCI controller; one for host
mode and another for device mode. So in order for PCI to
work in host mode, EP mode DT node should be disabled and in order to PCI to
work in EP mode, host mode DT node should be disabled. Host mode and EP
mode are mutually exclusive.
Example:
axi {
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.