Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml- Extension
.yaml- Size
- 1644 bytes
- Lines
- 64
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell CN10K LLC-TAD performance monitor
maintainers:
- Bhaskara Budiredla <bbudiredla@marvell.com>
description: |
The Tag-and-Data units (TADs) maintain coherence and contain CN10K
shared on-chip last level cache (LLC). The tad pmu measures the
performance of last-level cache. Each tad pmu supports up to eight
counters.
The DT setup comprises of number of tad blocks, the sizes of pmu
regions, tad blocks and overall base address of the HW.
properties:
compatible:
const: marvell,cn10k-tad-pmu
reg:
maxItems: 1
marvell,tad-cnt:
description: specifies the number of tads on the soc
$ref: /schemas/types.yaml#/definitions/uint32
marvell,tad-page-size:
description: specifies the size of each tad page
$ref: /schemas/types.yaml#/definitions/uint32
marvell,tad-pmu-page-size:
description: specifies the size of page that the pmu uses
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- marvell,tad-cnt
- marvell,tad-page-size
- marvell,tad-pmu-page-size
additionalProperties: false
examples:
- |
tad {
#address-cells = <2>;
#size-cells = <2>;
tad_pmu@80000000 {
compatible = "marvell,cn10k-tad-pmu";
reg = <0x87e2 0x80000000 0x0 0x1000>;
marvell,tad-cnt = <1>;
marvell,tad-page-size = <0x1000>;
marvell,tad-pmu-page-size = <0x1000>;
};
};
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.