Documentation/devicetree/bindings/perf/riscv,pmu.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/perf/riscv,pmu.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/perf/riscv,pmu.yaml
Extension
.yaml
Size
7156 bytes
Lines
161
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RISC-V SBI PMU events

maintainers:
  - Atish Patra <atishp@rivosinc.com>

description: |
  The SBI PMU extension allows supervisor software to configure, start and
  stop any performance counter at anytime. Thus, a user can leverage all
  capabilities of performance analysis tools, such as perf, if the SBI PMU
  extension is enabled. The following constraints apply:

    The platform must provide information about PMU event to counter mappings
    either via device tree or another way, specific to the platform.
    Without the event to counter mappings, the SBI PMU extension cannot be used.

    Platforms should provide information about the PMU event selector values
    that should be encoded in the expected value of MHPMEVENTx while configuring
    MHPMCOUNTERx for that specific event. The can either be done via device tree
    or another way, specific to the platform.
    The exact value to be written to MHPMEVENTx is completely dependent on the
    platform.

    For information on the SBI specification see the section "Performance
    Monitoring Unit Extension" of:
      https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc

properties:
  compatible:
    const: riscv,pmu

  riscv,event-to-mhpmevent:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    description:
      Represents an ONE-to-ONE mapping between a PMU event and the event
      selector value that the platform expects to be written to the MHPMEVENTx
      CSR for that event.
      The mapping is encoded in an matrix format where each element represents
      an event.
      This property shouldn't encode any raw hardware event.
    items:
      items:
        - description: event_idx, a 20-bit wide encoding of the event type and
            code. Refer to the SBI specification for a complete description of
            the event types and codes.
        - description: upper 32 bits of the event selector value for MHPMEVENTx
        - description: lower 32 bits of the event selector value for MHPMEVENTx

  riscv,event-to-mhpmcounters:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    description:
      Represents a MANY-to-MANY mapping between a range of events and all the
      MHPMCOUNTERx in a bitmap format that can be used to monitor these range
      of events. The information is encoded in an matrix format where each
      element represents a certain range of events and corresponding counters.
      This property shouldn't encode any raw event.
    items:
      items:
        - description: first event_idx of the range of events
        - description: last event_idx of the range of events
        - description: bitmap of MHPMCOUNTERx for this event

  riscv,raw-event-to-mhpmcounters:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    description:

Annotation

Implementation Notes