Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/phy/airoha,en7581-pcie-phy.yaml- Extension
.yaml- Size
- 1700 bytes
- Lines
- 70
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/phy/phy.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Airoha EN7581 PCI-Express PHY
maintainers:
- Lorenzo Bianconi <lorenzo@kernel.org>
description:
The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
properties:
compatible:
const: airoha,en7581-pcie-phy
reg:
items:
- description: PCIE analog base address
- description: PCIE lane0 base address
- description: PCIE lane1 base address
- description: PCIE lane0 detection time base address
- description: PCIE lane1 detection time base address
- description: PCIE Rx AEQ base address
reg-names:
items:
- const: csr-2l
- const: pma0
- const: pma1
- const: p0-xr-dtime
- const: p1-xr-dtime
- const: rx-aeq
"#phy-cells":
const: 0
required:
- compatible
- reg
- reg-names
- "#phy-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/phy/phy.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
phy@11e80000 {
compatible = "airoha,en7581-pcie-phy";
#phy-cells = <0>;
reg = <0x0 0x1fa5a000 0x0 0xfff>,
<0x0 0x1fa5b000 0x0 0xfff>,
<0x0 0x1fa5c000 0x0 0xfff>,
<0x0 0x1fc10044 0x0 0x4>,
<0x0 0x1fc30044 0x0 0x4>,
<0x0 0x1fc15030 0x0 0x104>;
reg-names = "csr-2l", "pma0", "pma1",
"p0-xr-dtime", "p1-xr-dtime",
"rx-aeq";
};
};
Annotation
- Immediate include surface: `dt-bindings/phy/phy.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.