Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml
Extension
.yaml
Size
4628 bytes
Lines
165
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY

maintainers:
  - Richard Zhu <hongxing.zhu@nxp.com>

properties:
  compatible:
    enum:
      - fsl,imx8qm-hsio
      - fsl,imx8qxp-hsio
  reg:
    items:
      - description: Base address and length of the PHY block
      - description: HSIO control and status registers(CSR) of the PHY
      - description: HSIO CSR of the controller bound to the PHY
      - description: HSIO CSR for MISC

  reg-names:
    items:
      - const: reg
      - const: phy
      - const: ctrl
      - const: misc

  "#phy-cells":
    const: 3
    description:
      The first defines lane index.
      The second defines the type of the PHY refer to the include phy.h.
      The third defines the controller index, indicated which controller
      is bound to the lane.

  clocks:
    minItems: 5
    maxItems: 14

  clock-names:
    minItems: 5
    maxItems: 14

  fsl,hsio-cfg:
    description: |
      Specifies the use case of the HSIO module in the hardware design.
      Regarding the design of i.MX8QM HSIO subsystem, HSIO module can be
      confiured as following three use cases.
      +---------------------------------------+
      |                  | i.MX8QM            |
      |------------------|--------------------|
      |                  | Lane0| Lane1| Lane2|
      |------------------|------|------|------|
      | pciea-x2-sata    | PCIEA| PCIEA| SATA |
      |------------------|------|------|------|
      | pciea-x2-pcieb   | PCIEA| PCIEA| PCIEB|
      |------------------|------|------|------|
      | pciea-pcieb-sata | PCIEA| PCIEB| SATA |
      +---------------------------------------+
    $ref: /schemas/types.yaml#/definitions/string
    enum: [ pciea-x2-sata, pciea-x2-pcieb, pciea-pcieb-sata]
    default: pciea-pcieb-sata

  fsl,refclk-pad-mode:
    description:
      Specifies the mode of the refclk pad used. INPUT(PHY refclock is
      provided externally via the refclk pad) or OUTPUT(PHY refclock is

Annotation

Implementation Notes