Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
Extension
.yaml
Size
2638 bytes
Lines
122
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek High Definition Multimedia Interface (HDMI) PHY

maintainers:
  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  - Philipp Zabel <p.zabel@pengutronix.de>
  - Chunfeng Yun <chunfeng.yun@mediatek.com>

description: |
  The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
  output and drives the HDMI pads.

properties:
  $nodename:
    pattern: "^hdmi-phy@[0-9a-f]+$"

  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt7623-hdmi-phy
          - const: mediatek,mt2701-hdmi-phy
      - items:
          - enum:
              - mediatek,mt8188-hdmi-phy
          - const: mediatek,mt8195-hdmi-phy
      - const: mediatek,mt2701-hdmi-phy
      - const: mediatek,mt8173-hdmi-phy
      - const: mediatek,mt8195-hdmi-phy

  reg:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: PLL reference clock
      - description: HDMI 26MHz clock
      - description: HDMI PLL1 clock
      - description: HDMI PLL2 clock

  clock-names:
    minItems: 1
    items:
      - const: pll_ref
      - const: 26m
      - const: pll1
      - const: pll2

  clock-output-names:
    maxItems: 1

  "#phy-cells":
    const: 0

  "#clock-cells":
    const: 0

  mediatek,ibias:
    description:
      TX DRV bias current for < 1.65Gbps
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 63

Annotation

Implementation Notes