Documentation/devicetree/bindings/phy/mediatek,tphy.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
Extension
.yaml
Size
10312 bytes
Lines
335
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek T-PHY Controller

maintainers:
  - Chunfeng Yun <chunfeng.yun@mediatek.com>

description: |
  The T-PHY controller supports physical layer functionality for a number of
  controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.

  Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
  T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
  -----------------------------------
  Version 1:
  port        offset    bank
  shared      0x0000    SPLLC
              0x0100    FMREG
  u2 port0    0x0800    U2PHY_COM
  u3 port0    0x0900    U3PHYD
              0x0a00    U3PHYD_BANK2
              0x0b00    U3PHYA
              0x0c00    U3PHYA_DA
  u2 port1    0x1000    U2PHY_COM
  u3 port1    0x1100    U3PHYD
              0x1200    U3PHYD_BANK2
              0x1300    U3PHYA
              0x1400    U3PHYA_DA
  u2 port2    0x1800    U2PHY_COM
              ...

  Version 2/3:
  port        offset    bank
  u2 port0    0x0000    MISC
              0x0100    FMREG
              0x0300    U2PHY_COM
  u3 port0    0x0700    SPLLC
              0x0800    CHIP
              0x0900    U3PHYD
              0x0a00    U3PHYD_BANK2
              0x0b00    U3PHYA
              0x0c00    U3PHYA_DA
  u2 port1    0x1000    MISC
              0x1100    FMREG
              0x1300    U2PHY_COM
  u3 port1    0x1700    SPLLC
              0x1800    CHIP
              0x1900    U3PHYD
              0x1a00    U3PHYD_BANK2
              0x1b00    U3PHYA
              0x1c00    U3PHYA_DA
  u2 port2    0x2000    MISC
              ...

  SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
  into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
  added on V2; the FMREG bank for slew rate calibration is not used anymore
  and reserved on V3;

properties:
  $nodename:
    pattern: "^t-phy(@[0-9a-f]+)?$"

  compatible:
    oneOf:

Annotation

Implementation Notes