Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
Extension
.yaml
Size
3821 bytes
Lines
154
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip SoC Naneng Combo Phy

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    enum:
      - rockchip,rk3528-naneng-combphy
      - rockchip,rk3562-naneng-combphy
      - rockchip,rk3568-naneng-combphy
      - rockchip,rk3576-naneng-combphy
      - rockchip,rk3588-naneng-combphy

  reg:
    maxItems: 1

  clocks:
    items:
      - description: reference clock
      - description: apb clock
      - description: pipe clock

  clock-names:
    items:
      - const: ref
      - const: apb
      - const: pipe

  resets:
    minItems: 1
    maxItems: 2

  reset-names:
    minItems: 1
    items:
      - const: phy
      - const: apb

  phy-supply:
    description: Single PHY regulator

  power-domains:
    maxItems: 1

  rockchip,enable-ssc:
    type: boolean
    description:
      The option SSC can be enabled for U3, SATA and PCIE.
      Most commercially available platforms use SSC to reduce EMI.

  rockchip,ext-refclk:
    type: boolean
    description:
      Many PCIe connections, especially backplane connections,
      require a synchronous reference clock between the two link partners.
      To achieve this a common clock source, referred to as REFCLK in
      the PCI Express Card Electromechanical Specification,
      should be used by both ends of the PCIe link.
      In PCIe mode one can choose to use an internal or an external reference
      clock.
      By default the internal clock is selected. The PCIe PHY provides a 100MHz
      differential clock output(optional with SSC) for system applications.
      When selecting this option an externally 100MHz differential

Annotation

Implementation Notes