Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
Extension
.yaml
Size
4495 bytes
Lines
153
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip USBDP Combo PHY with Samsung IP block

maintainers:
  - Frank Wang <frank.wang@rock-chips.com>
  - Zhang Yubing <yubing.zhang@rock-chips.com>

properties:
  compatible:
    enum:
      - rockchip,rk3576-usbdp-phy
      - rockchip,rk3588-usbdp-phy

  reg:
    maxItems: 1

  "#phy-cells":
    description: |
      Cell allows setting the type of the PHY. Possible values are:
      - PHY_TYPE_USB3
      - PHY_TYPE_DP
    const: 1

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: refclk
      - const: immortal
      - const: pclk
      - const: utmi

  resets:
    maxItems: 5

  reset-names:
    items:
      - const: init
      - const: cmn
      - const: lane
      - const: pcs_apb
      - const: pma_apb

  phy-supply:
    description: Single PHY regulator

  rockchip,dp-lane-mux:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 2
    maxItems: 4
    items:
      maximum: 3
    description:
      An array of physical Type-C lanes indexes. Position of an entry
      determines the DisplayPort (DP) lane index, while the value of an entry
      indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
      e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
      3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
      lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
      <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
      phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
      DP lanes are mapped by DisplayPort Alt mode, this property is not needed.

  rockchip,u2phy-grf:

Annotation

Implementation Notes