Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/phy/realtek,usb3phy.yaml
Extension
.yaml
Size
3187 bytes
Lines
108
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2023 Realtek Semiconductor Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/realtek,usb3phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Realtek DHC SoCs USB 3.0 PHY

maintainers:
  - Stanley Chang <stanley_chang@realtek.com>

description: |
  Realtek USB 3.0 PHY support the digital home center (DHC) RTD series SoCs.
  The USB 3.0 PHY driver is designed to support the XHCI controller. The SoCs
  support multiple XHCI controllers. One PHY device node maps to one XHCI
  controller.

  RTD1295/RTD1619 SoCs USB
  The USB architecture includes three XHCI controllers.
  Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
  controllers.
  XHCI controller#0 -- usb2phy -- phy#0
                    |- usb3phy -- phy#0
  XHCI controller#1 -- usb2phy -- phy#0
  XHCI controller#2 -- usb2phy -- phy#0
                    |- usb3phy -- phy#0

  RTD1319/RTD1619b SoCs USB
  The USB architecture includes three XHCI controllers.
  Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2.
  XHCI controller#0 -- usb2phy -- phy#0
  XHCI controller#1 -- usb2phy -- phy#0
  XHCI controller#2 -- usb2phy -- phy#0
                    |- usb3phy -- phy#0

  RTD1319d SoCs USB
  The USB architecture includes three XHCI controllers.
  Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0.
  XHCI controller#0 -- usb2phy -- phy#0
                    |- usb3phy -- phy#0
  XHCI controller#1 -- usb2phy -- phy#0
  XHCI controller#2 -- usb2phy -- phy#0

properties:
  compatible:
    enum:
      - realtek,rtd1295-usb3phy
      - realtek,rtd1319-usb3phy
      - realtek,rtd1319d-usb3phy
      - realtek,rtd1619-usb3phy
      - realtek,rtd1619b-usb3phy

  reg:
    maxItems: 1

  "#phy-cells":
    const: 0

  nvmem-cells:
    maxItems: 1
    description: A phandle to the tx lfps swing trim data provided by
      a nvmem device, if unspecified, default values shall be used.

  nvmem-cell-names:
    items:
      - const: usb_u3_tx_lfps_swing_trim

  realtek,amplitude-control-coarse-tuning:
    description:

Annotation

Implementation Notes