Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml- Extension
.yaml- Size
- 2608 bytes
- Lines
- 117
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/rk3568-cru.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip PCIe v3 phy
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
enum:
- rockchip,rk3568-pcie3-phy
- rockchip,rk3588-pcie3-phy
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
maxItems: 3
data-lanes:
description: which lanes (by position) should be mapped to which
controller (value). 0 means lane disabled, higher value means used.
(controller-number +1 )
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 16
items:
minimum: 0
maximum: 16
"#phy-cells":
const: 0
resets:
maxItems: 1
reset-names:
const: phy
phy-supply:
description: Single PHY regulator
rockchip,phy-grf:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the syscon managing the phy "general register files"
rockchip,pipe-grf:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the syscon managing the pipe "general register files"
rockchip,rx-common-refclk-mode:
description: which lanes (by position) should be configured to run in
RX common reference clock mode. 0 means disabled, 1 means enabled.
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 16
items:
minimum: 0
maximum: 1
required:
Annotation
- Immediate include surface: `dt-bindings/clock/rk3568-cru.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.