Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml- Extension
.yaml- Size
- 3123 bytes
- Lines
- 120
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/st,stm32mp25-rcc.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/reset/st,stm32mp25-rcc.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/st,stm32mp25-combophy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32MP25 USB3/PCIe COMBOPHY
maintainers:
- Christian Bruel <christian.bruel@foss.st.com>
description:
Single lane PHY shared (exclusive) between the USB3 and PCIe controllers.
Supports 5Gbit/s for USB3 and PCIe gen2 or 2.5Gbit/s for PCIe gen1.
properties:
compatible:
const: st,stm32mp25-combophy
reg:
maxItems: 1
"#phy-cells":
const: 1
clocks:
minItems: 2
items:
- description: apb Bus clock mandatory to access registers.
- description: ker Internal RCC reference clock for USB3 or PCIe
- description: pad Optional on board clock input for PCIe only. Typically an
external 100Mhz oscillator wired on dedicated CLKIN pad. Used as reference
clock input instead of the ker
clock-names:
minItems: 2
items:
- const: apb
- const: ker
- const: pad
resets:
maxItems: 1
reset-names:
const: phy
power-domains:
maxItems: 1
wakeup-source: true
interrupts:
maxItems: 1
description: interrupt used for wakeup
access-controllers:
maxItems: 1
description: Phandle to the rifsc device to check access right.
st,ssc-on:
$ref: /schemas/types.yaml#/definitions/flag
description:
A property whose presence indicates that the Spread Spectrum Clocking is active.
st,rx-equalizer:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
default: 2
Annotation
- Immediate include surface: `dt-bindings/clock/st,stm32mp25-rcc.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/reset/st,stm32mp25-rcc.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.