Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
Extension
.yaml
Size
2389 bytes
Lines
106
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx ZynqMP Gigabit Transceiver PHY

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

description: |
  This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
  GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
  Ethernet SGMII controllers.

properties:
  "#phy-cells":
    const: 4
    description: |
      The cells contain the following arguments.

      - description: The GTR lane
        minimum: 0
        maximum: 3
      - description: The PHY type
        enum:
          - PHY_TYPE_DP
          - PHY_TYPE_PCIE
          - PHY_TYPE_SATA
          - PHY_TYPE_SGMII
          - PHY_TYPE_USB3
      - description: The PHY instance
        minimum: 0
        maximum: 1 # for DP, SATA or USB
        maximum: 3 # for PCIE or SGMII
      - description: The reference clock number
        minimum: 0
        maximum: 3

  compatible:
    enum:
      - xlnx,zynqmp-psgtr-v1.1
      - xlnx,zynqmp-psgtr

  clocks:
    minItems: 1
    maxItems: 4
    description: |
      Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
      inputs shall not have an entry.

  clock-names:
    minItems: 1
    maxItems: 4
    items:
      pattern: "^ref[0-3]$"

  reg:
    items:
      - description: SERDES registers block
      - description: SIOU registers block

  reg-names:
    items:
      - const: serdes
      - const: siou

  xlnx,tx-termination-fix:
    description: |

Annotation

Implementation Notes