Documentation/devicetree/bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml
Extension
.yaml
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4807 bytes
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185
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip PIO3 Pinmux Controller

maintainers:
  - Manikandan Muralidharan <manikandan.m@microchip.com>

description:
  The AT91 Pinmux Controller, enables the IC to share one PAD to several
  functional blocks. The sharing is done by multiplexing the PAD input/output
  signals. For each PAD there are up to 8 muxing options (called periph modes).
  Since different modules require different PAD settings (like pull up, keeper,
  etc) the controller controls also the PAD settings parameters.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - atmel,at91rm9200-pinctrl
              - atmel,at91sam9x5-pinctrl
              - atmel,sama5d3-pinctrl
              - microchip,sam9x60-pinctrl
          - const: simple-mfd
      - items:
          - enum:
              - microchip,sam9x7-pinctrl
          - const: microchip,sam9x60-pinctrl
          - const: simple-mfd

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  ranges: true

  atmel,mux-mask:
    $ref: /schemas/types.yaml#/definitions/uint32-matrix
    description: |
      Array of mask (periph per bank) to describe if a pin can be
      configured in this periph mode. All the periph and bank need to
      be described.

      #How to create such array:

      Each column will represent the possible peripheral of the pinctrl
      Each line will represent a pio bank

      #Example:

      In at91sam9260.dtsi,
      Peripheral: 2 ( A and B)
      Bank: 3 (A, B and C)

      #    A          B
      0xffffffff 0xffc00c3b  # pioA
      0xffffffff 0x7fff3ccf  # pioB
      0xffffffff 0x007fffff  # pioC

      For each peripheral/bank we will describe in a u32 if a pin can be
      configured in it by putting 1 to the pin bit (1 << pin)

      Let's take the pioA on peripheral B whose value is 0xffc00c3b
      From the datasheet Table 10-2.

Annotation

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