Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt

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Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt
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Support Tooling And Documentation
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Support Tooling And Documentation: documentation
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Imagination Technologies Pistachio SoC pin controllers
======================================================

The pin controllers on Pistachio are a combined GPIO controller, (GPIO)
interrupt controller, and pinmux + pinconf device. The system ("east") pin
controller on Pistachio has 99 pins, 90 of which are MFIOs which can be
configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs
each. The GPIO banks are represented as sub-nodes of the pad controller node.

Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
../interrupt-controller/interrupts.txt for generic information regarding
pin controller, GPIO, and interrupt bindings.

Required properties for pin controller node:
--------------------------------------------
 - compatible: "img,pistachio-system-pinctrl".
 - reg: Address range of the pinctrl registers.

Required properties for GPIO bank sub-nodes:
--------------------------------------------
 - interrupts: Interrupt line for the GPIO bank.
 - gpio-controller: Indicates the device is a GPIO controller.
 - #gpio-cells: Must be two. The first cell is the GPIO pin number and the
   second cell indicates the polarity. See <dt-bindings/gpio/gpio.h> for
   a list of possible values.
 - interrupt-controller: Indicates the device is an interrupt controller.
 - #interrupt-cells: Must be two. The first cell is the GPIO pin number and
   the second cell encodes the interrupt flags. See
   <dt-bindings/interrupt-controller/irq.h> for a list of valid flags.

Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1.

Required properties for pin configuration sub-nodes:
----------------------------------------------------
 - pins: List of pins to which the configuration applies. See below for a
   list of possible pins.

Optional properties for pin configuration sub-nodes:
----------------------------------------------------
 - function: Mux function for the specified pins. This is not applicable for
   non-MFIO pins. See below for a list of valid functions for each pin.
 - bias-high-impedance: Enable high-impedance mode.
 - bias-pull-up: Enable weak pull-up.
 - bias-pull-down: Enable weak pull-down.
 - bias-bus-hold: Enable bus-keeper mode.
 - drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12.
 - input-schmitt-enable: Enable Schmitt trigger.
 - input-schmitt-disable: Disable Schmitt trigger.
 - slew-rate: Slew rate control. 0 for slow, 1 for fast.

Pin		Functions
---		---------
mfio0		spim1
mfio1		spim1, spim0, uart1
mfio2		spim1, spim0, uart1
mfio3		spim1
mfio4		spim1
mfio5		spim1
mfio6		spim1
mfio7		spim1
mfio8		spim0
mfio9		spim0
mfio10		spim0
mfio11		spis
mfio12		spis
mfio13		spis
mfio14		spis
mfio15		sdhost, mips_trace_clk, mips_trace_data
mfio16		sdhost, mips_trace_dint, mips_trace_data
mfio17		sdhost, mips_trace_trigout, mips_trace_data

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