Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml- Extension
.yaml- Size
- 5833 bytes
- Lines
- 203
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/renesas,r9a09g077-cpg-mssr.hdt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller.
Pin multiplexing and GPIO configuration are performed on a per-pin basis.
Each port supports up to 8 pins, each configurable for either GPIO (port mode)
or alternate function mode. Each pin supports function mode values ranging from
0x0 to 0x2A, allowing selection from up to 43 different functions.
properties:
compatible:
enum:
- renesas,r9a09g077-pinctrl # RZ/T2H
- renesas,r9a09g087-pinctrl # RZ/N2H
reg:
minItems: 1
items:
- description: Non-safety I/O Port base
- description: Safety I/O Port safety region base
- description: Safety I/O Port Non-safety region base
reg-names:
minItems: 1
items:
- const: nsr
- const: srs
- const: srn
gpio-controller: true
'#gpio-cells':
const: 2
description:
The first cell contains the global GPIO port index, constructed using the
RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
(e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer
flag. Use the macros defined in include/dt-bindings/gpio/gpio.h.
gpio-ranges:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
description:
The first cell contains the global GPIO port index, constructed using the
RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
and the second cell is used to specify the flag.
E.g. "interrupts = <RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>;" if P08_6 is
being used as an interrupt.
clocks:
maxItems: 1
power-domains:
maxItems: 1
definitions:
renesas-rzt2h-n2h-pins-node:
Annotation
- Immediate include surface: `dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h`, `dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.