Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml
Extension
.yaml
Size
6896 bytes
Lines
188
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/A1 combined Pin and GPIO controller

maintainers:
  - Jacopo Mondi <jacopo+renesas@jmondi.org>
  - Geert Uytterhoeven <geert+renesas@glider.be>

description:
  The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
  controller, named "Ports" in the hardware reference manual.
  Pin multiplexing and GPIO configuration is performed on a per-pin basis
  writing configuration values to per-port register sets.
  Each "port" features up to 16 pins, each of them configurable for GPIO
  function (port mode) or in alternate function mode.
  Up to 8 different alternate function modes exist for each single pin.

properties:
  compatible:
    oneOf:
      - const: renesas,r7s72100-ports     # RZ/A1H
      - items:
          - const: renesas,r7s72101-ports # RZ/A1M
          - const: renesas,r7s72100-ports # fallback
      - const: renesas,r7s72102-ports     # RZ/A1L

  reg:
    maxItems: 1

allOf:
  - $ref: pinctrl.yaml#

required:
  - compatible
  - reg

patternProperties:
  "^gpio-[0-9]*$":
    type: object
    additionalProperties: false

    description:
      Each port of the r7s72100 pin controller hardware is itself a GPIO
      controller.
      Different SoCs have different numbers of available pins per port, but
      generally speaking, each of them can be configured in GPIO ("port") mode
      on this hardware.
      Describe GPIO controllers using sub-nodes with the following properties.

    properties:
      gpio-controller: true

      '#gpio-cells':
        const: 2

      gpio-ranges:
        maxItems: 1

    required:
      - gpio-controller
      - '#gpio-cells'
      - gpio-ranges

additionalProperties:
  anyOf:
    - type: object

Annotation

Implementation Notes