Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
Extension
.yaml
Size
7898 bytes
Lines
262
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller

maintainers:
  - Geert Uytterhoeven <geert+renesas@glider.be>
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

description:
  The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
  GPIO controller.
  Pin multiplexing and GPIO configuration is performed on a per-pin basis.
  Each port features up to 8 pins, each of them configurable for GPIO function
  (port mode) or in alternate function mode.
  Up to 8 different alternate function modes exist for each single pin.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
              - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
              - renesas,r9a08g045-pinctrl # RZ/G3S
              - renesas,r9a08g046-pinctrl # RZ/G3L
              - renesas,r9a09g047-pinctrl # RZ/G3E
              - renesas,r9a09g056-pinctrl # RZ/V2N
              - renesas,r9a09g057-pinctrl # RZ/V2H(P)

      - items:
          - enum:
              - renesas,r9a07g054-pinctrl     # RZ/V2L
          - const: renesas,r9a07g044-pinctrl  # RZ/G2{L,LC} fallback for RZ/V2L

  reg:
    maxItems: 1

  gpio-controller: true

  '#gpio-cells':
    const: 2
    description:
      The first cell contains the global GPIO port index, constructed using the
      RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
      second cell represents consumer flag as mentioned in ../gpio/gpio.txt
      E.g. "RZG2L_GPIO(39, 1)" for P39_1.

  gpio-ranges:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    const: 2
    description:
      The first cell contains the global GPIO port index, constructed using the
      RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
      second cell is used to specify the flag.
      E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is
      being used as an interrupt.

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

Annotation

Implementation Notes