Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml
Extension
.yaml
Size
4158 bytes
Lines
127
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/N1 Pin Controller

maintainers:
  - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
  - Geert Uytterhoeven <geert+renesas@glider.be>

properties:
  compatible:
    items:
      - const: renesas,r9a06g032-pinctrl # RZ/N1D
      - const: renesas,rzn1-pinctrl   # Generic RZ/N1

  reg:
    items:
      - description: GPIO Multiplexing Level1 Register Block
      - description: GPIO Multiplexing Level2 Register Block

  clocks:
    maxItems: 1

  clock-names:
    const: bus
    description:
      The bus clock, sometimes described as pclk, for register accesses.

allOf:
  - $ref: pinctrl.yaml#

required:
  - compatible
  - reg
  - clocks
  - clock-names

additionalProperties:
  anyOf:
    - type: object
      allOf:
        - $ref: pincfg-node.yaml#
        - $ref: pinmux-node.yaml#

      description:
        A pin multiplexing sub-node describes how to configure a set of (or a
        single) pin in some desired alternate function mode.
        A single sub-node may define several pin configurations.

      properties:
        pinmux:
          description: |
            Integer array representing pin number and pin multiplexing
            configuration.
            When a pin has to be configured in alternate function mode, use
            this property to identify the pin by its global index, and provide
            its alternate function configuration number along with it.
            When multiple pins are required to be configured as part of the
            same alternate function they shall be specified as members of the
            same argument list of a single "pinmux" property.
            Integers values in the "pinmux" argument list are assembled as:
            (PIN | MUX_FUNC << 8)
            where PIN directly corresponds to the pl_gpio pin number and
            MUX_FUNC is one of the alternate function identifiers defined in:
            <include/dt-bindings/pinctrl/rzn1-pinctrl.h>
            These identifiers collapse the IO Multiplex Configuration Level 1
            and Level 2 numbers that are detailed in the hardware reference

Annotation

Implementation Notes