Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml- Extension
.yaml- Size
- 5915 bytes
- Lines
- 168
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/pinctrl/rzv2m-pinctrl.hdt-bindings/clock/r9a09g011-cpg.hdt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/V2M combined Pin and GPIO controller
maintainers:
- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The Renesas RZ/V2M SoC features a combined Pin and GPIO controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 16 pins, each of them configurable for GPIO function
(port mode) or in alternate function mode.
Up to 8 different alternate function modes exist for each single pin.
properties:
compatible:
const: renesas,r9a09g011-pinctrl # RZ/V2M
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
const: 2
description:
The first cell contains the global GPIO port index, constructed using the
RZV2M_GPIO() helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h> and the
second cell represents consumer flag as mentioned in ../gpio/gpio.txt
E.g. "RZV2M_GPIO(8, 1)" for P8_1.
gpio-ranges:
maxItems: 1
interrupts:
description: INEXINT[0..38] corresponding to individual pin inputs.
maxItems: 39
clocks:
maxItems: 1
power-domains:
maxItems: 1
resets:
maxItems: 1
additionalProperties:
anyOf:
- type: object
additionalProperties: false
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
Pin controller client devices use pin configuration subnodes (children
and grandchildren) for desired pin configuration.
Client device subnodes use below standard properties.
properties:
pinmux:
description:
Values are constructed from GPIO port number, pin number, and
alternate function configuration number using the RZV2M_PORT_PINMUX()
Annotation
- Immediate include surface: `dt-bindings/pinctrl/rzv2m-pinctrl.h`, `dt-bindings/clock/r9a09g011-cpg.h`, `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.