Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml- Extension
.yaml- Size
- 5113 bytes
- Lines
- 196
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.hdt-bindings/pinctrl/rockchip.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip Pinmux Controller
maintainers:
- Heiko Stuebner <heiko@sntech.de>
description: |
The Rockchip Pinmux Controller enables the IC to share one PAD
to several functional blocks. The sharing is done by multiplexing
the PAD input/output signals. For each PAD there are several muxing
options with option 0 being used as a GPIO.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The Rockchip pin configuration node is a node of a group of pins which can be
used for a specific device or function. This node represents both mux and
config of the pins in that group. The 'pins' selects the function mode
(also named pin mode) this pin can work on and the 'config' configures
various pad settings such as pull-up, etc.
The pins are grouped into up to 9 individual pin banks which need to be
defined as gpio sub-nodes of the pinmux controller.
properties:
compatible:
enum:
- rockchip,px30-pinctrl
- rockchip,rk2928-pinctrl
- rockchip,rk3036-pinctrl
- rockchip,rk3066a-pinctrl
- rockchip,rk3066b-pinctrl
- rockchip,rk3128-pinctrl
- rockchip,rk3188-pinctrl
- rockchip,rk3228-pinctrl
- rockchip,rk3288-pinctrl
- rockchip,rk3308-pinctrl
- rockchip,rk3328-pinctrl
- rockchip,rk3368-pinctrl
- rockchip,rk3399-pinctrl
- rockchip,rk3506-pinctrl
- rockchip,rk3528-pinctrl
- rockchip,rk3562-pinctrl
- rockchip,rk3568-pinctrl
- rockchip,rk3576-pinctrl
- rockchip,rk3588-pinctrl
- rockchip,rv1103b-pinctrl
- rockchip,rv1108-pinctrl
- rockchip,rv1126-pinctrl
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The phandle of the syscon node for the GRF registers.
rockchip,pmu:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The phandle of the syscon node for the PMU registers,
as some SoCs carry parts of the iomux controller registers there.
Required for at least rk3188 and rk3288. On the rk3368 this should
point to the PMUGRF syscon.
"#address-cells":
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/pinctrl/rockchip.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.