Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
Extension
.yaml
Size
9957 bytes
Lines
307
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: StarFive JH7100 Pin Controller

description: |
  Bindings for the JH7100 RISC-V SoC from StarFive Ltd.

  Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]
  and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have
  configurable bias, drive strength, schmitt trigger etc. The SoC has an
  interesting 2-layered approach to pin muxing best illustrated by the diagram
  below.

                          Signal group 0, 1, ... or 6
                                 ___|___
                                |       |
    LCD output -----------------|       |
    CMOS Camera interface ------|       |--- PAD_GPIO[0]
    Ethernet PHY interface -----|  MUX  |--- PAD_GPIO[1]
      ...                       |       |      ...
                                |       |--- PAD_GPIO[63]
     -------- GPIO0 ------------|       |
    |  -------|-- GPIO1 --------|       |--- PAD_FUNC_SHARE[0]
    | |       |   |             |       |--- PAD_FUNC_SHARE[1]
    | |       |   |  ...        |       |       ...
    | |       |   |             |       |--- PAD_FUNC_SHARE[141]
    | |  -----|---|-- GPIO63 ---|       |
    | | |     |   |   |          -------
    UART0     UART1 --

  The big MUX in the diagram only has 7 different ways of mapping peripherals
  on the left to pins on the right. StarFive calls the 7 configurations "signal
  groups".
  However some peripherals have their I/O go through the 64 "GPIOs". The
  diagram only shows UART0 and UART1, but this also includes a number of other
  UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64
  GPIOs such that any GPIO can be set up to be controlled by any of the
  peripherals.
  Note that signal group 0 doesn't map any of the GPIOs to pins, and only
  signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63].

maintainers:
  - Emil Renner Berthing <kernel@esmil.dk>
  - Drew Fustini <drew@beagleboard.org>

properties:
  compatible:
    const: starfive,jh7100-pinctrl

  reg:
    minItems: 2
    maxItems: 2

  reg-names:
    items:
      - const: gpio
      - const: padctl

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  gpio-controller: true

Annotation

Implementation Notes