Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml- Extension
.yaml- Size
- 2924 bytes
- Lines
- 125
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive JH7110 AON Pin Controller
description: |
Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
Out of the SoC's many pins only the ones named PAD_RGPIO0 to PAD_RGPIO3
can be multiplexed and have configurable bias, drive strength,
schmitt trigger etc.
Some peripherals such as PWM have their I/O go through the 4 "GPIOs".
maintainers:
- Hal Feng <hal.feng@starfivetech.com>
properties:
compatible:
const: starfive,jh7110-aon-pinctrl
reg:
maxItems: 1
resets:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
const: 2
patternProperties:
'-[0-9]+$':
type: object
additionalProperties: false
patternProperties:
'-pins$':
type: object
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to
muxer configuration, bias, input enable/disable, input schmitt
trigger enable/disable, slew-rate and drive strength.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
additionalProperties: false
properties:
pinmux:
description: |
The list of GPIOs and their mux settings that properties in the
node apply to. This should be set using the GPIOMUX macro.
bias-disable: true
bias-pull-up:
type: boolean
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.