Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml

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Linux kernel
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Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml
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.yaml
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Support Tooling And Documentation
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Documentation
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Support Tooling And Documentation: configuration, schema, or hardware description
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) Sunplus Co., Ltd.
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sunplus SP7021 Pin Controller

maintainers:
  - Dvorkin Dmitry <dvorkin@tibbo.com>
  - Wells Lu <wellslutw@gmail.com>

description: |
  The Sunplus SP7021 pin controller is used to control SoC pins. Please
  refer to pinctrl-bindings.txt in this directory for details of the common
  pinctrl bindings used by client devices.

  SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All
  are multiplexed with some special function pins. SP7021 has 3 types of
  special function pins:

  (1) function-group pins:
      Ex 1 (SPI-NOR flash):
        If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87
        will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79
        and 81 will be pins of SPI-NOR flash.

      Ex 2 (UART_0):
        If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and
        RX pins of UART_0 (UART channel 0).

      Ex 3 (eMMC):
        If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77,
        78, 79, 80, 81 will be pins of an eMMC device.

      Properties "function" and "groups" are used to select function-group
      pins.

  (2) fully pin-mux (like phone exchange mux) pins:
      GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of
      SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.)
      can be routed to any pins of fully pin-mux pins.

      Ex 1 (UART channel 1):
        If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be
        routed to GPIO 10 (3 - 1 + 8 = 10).
        If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be
        routed to GPIO 11 (4 - 1 + 8 = 11).
        If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will
        be routed to GPIO 12 (5 - 1 + 8 = 12).
        If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will
        be routed to GPIO 13 (6 - 1 + 8 = 13).

      Ex 2 (I2C channel 0):
        If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will
        be routed to GPIO 27 (20 - 1 + 8 = 27).
        If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0
        will be routed to GPIO 28 (21 - 1 + 9 = 28).

      Totally, SP7021 has 120 peripheral pins. The peripheral pins can be
      routed to any of 64 'fully pin-mux' pins.

  (3) I/O processor pins
      SP7021 has a built-in I/O processor.
      Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor.

  Vendor property "sunplus,pins" is used to select "fully pin-mux" pins,
  "I/O processor pins" and "digital GPIO" pins.

Annotation

Implementation Notes