Documentation/devicetree/bindings/pinctrl/xlnx,pinctrl-zynq.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pinctrl/xlnx,pinctrl-zynq.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/pinctrl/xlnx,pinctrl-zynq.yaml- Extension
.yaml- Size
- 7783 bytes
- Lines
- 211
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/pinctrl/pinctrl-zynq.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/xlnx,pinctrl-zynq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Pinctrl
maintainers:
- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
description: |
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
Zynq's pin configuration nodes act as a container for an arbitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, slew rate, etc.
Each configuration node can consist of multiple nodes describing the pinmux and
pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
properties:
compatible:
const: xlnx,pinctrl-zynq
reg:
description: Specifies the base address and size of the SLCR space.
maxItems: 1
syscon:
description:
phandle to the SLCR.
patternProperties:
'^(.*-)?(default|gpio-grp)$':
type: object
patternProperties:
'^mux':
type: object
description:
Pinctrl node's client devices use subnodes for pin muxes,
which in turn use below standard properties.
$ref: pinmux-node.yaml#
properties:
groups:
description:
List of groups to select (either this or "pins" must be
specified), available groups for this subnode.
items:
enum: [ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp,
mdio1_0_grp, qspi0_0_grp, qspi1_0_grp, qspi_fbclk,
qspi_cs1_grp, spi0_0_grp, spi0_1_grp, spi0_2_grp,
spi0_0_ss0, spi0_0_ss1, spi0_0_ss2, spi0_1_ss0,
spi0_1_ss1, spi0_1_ss2, spi0_2_ss0, spi0_2_ss1,
spi0_2_ss2, spi1_0_grp, spi1_1_grp, spi1_2_grp,
spi1_3_grp, spi1_0_ss0, spi1_0_ss1, spi1_0_ss2,
spi1_1_ss0, spi1_1_ss1, spi1_1_ss2, spi1_2_ss0,
spi1_2_ss1, spi1_2_ss2, spi1_3_ss0, spi1_3_ss1,
spi1_3_ss2, sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, sdio1_3_grp,
sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp,
Annotation
- Immediate include surface: `dt-bindings/pinctrl/pinctrl-zynq.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.