Documentation/devicetree/bindings/power/reset/ocelot-reset.txt

File Facts

System

Linux kernel

Corpus path

Documentation/devicetree/bindings/power/reset/ocelot-reset.txt

Extension

.txt

Size

472 bytes

Lines

20

Domain

Support Tooling And Documentation

Bucket

Documentation

Inferred role

Support Tooling And Documentation: documentation

Status

atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

• Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

Microsemi Ocelot reset controller

The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
SoC core.

The reset registers are both present in the MSCC vcoreiii MIPS and
microchip Sparx5 armv8 SoC's.

Required Properties:

 - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
   "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"

Example:
	reset@1070008 {
		compatible = "mscc,ocelot-chip-reset";
		reg = <0x1070008 0x4>;
	};

Annotation

• Atlas domain: Support Tooling And Documentation / Documentation.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.