Documentation/devicetree/bindings/powerpc/fsl/cpus.txt

File Facts

System

Linux kernel

Corpus path

Documentation/devicetree/bindings/powerpc/fsl/cpus.txt

Extension

.txt

Size

1457 bytes

Lines

34

Domain

Support Tooling And Documentation

Bucket

Documentation

Inferred role

Support Tooling And Documentation: documentation

Status

atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

• Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

===================================================================
Power Architecture CPU Binding
Copyright 2013 Freescale Semiconductor Inc.

Power Architecture CPUs in Freescale SOCs are represented in device trees as
per the definition in the Devicetree Specification.

In addition to the Devicetree Specification definitions, the properties
defined below may be present on CPU nodes.

PROPERTIES

   - fsl,eref-*
        Usage: optional
        Value type: <empty>
        Definition: The EREF (EREF: A Programmer.s Reference Manual for
	Freescale Power Architecture) defines the architecture for Freescale
	Power CPUs.  The EREF defines some architecture categories not defined
	by the Power ISA.  For these EREF-specific categories, the existence of
	a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
	name with all uppercase letters converted to lowercase, indicates that
	the category is supported by the implementation.

    - fsl,portid-mapping
	Usage: optional
	Value type: <u32>
	Definition: The Coherency Subdomain ID Port Mapping Registers and
	Snoop ID Port Mapping registers, which are part of the CoreNet
	Coherency fabric (CCF), provide a CoreNet Coherency Subdomain
	ID/CoreNet Snoop ID to cpu mapping functions.  Certain bits from
	these registers should be set if the corresponding CPU should be
	snooped.  This property defines a bitmask which selects the bit
	that should be set if this cpu should be snooped.

Annotation

• Atlas domain: Support Tooling And Documentation / Documentation.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.