Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt

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Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt
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===============================================================================
Freescale Interlaken Look-Aside Controller Device Bindings
Copyright 2012 Freescale Semiconductor Inc.

CONTENTS
  - Interlaken Look-Aside Controller (LAC) Node
  - Example LAC Node
  - Interlaken Look-Aside Controller (LAC) Software Portal Node
  - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
  - Example LAC SWP Node with Child Nodes

==============================================================================
Interlaken Look-Aside Controller (LAC) Node

DESCRIPTION

The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
facilitate interoperability between a data path device and a look-aside
co-processor, the Interlaken Look-Aside protocol is defined for short
transaction-related transfers. Although based on the Interlaken protocol,
Interlaken Look-Aside is not directly compatible with Interlaken and can be
considered a different operation mode.

The Interlaken LA controller connects internal platform to Interlaken serial
interface. It accepts LA command through software portals, which are system
memory mapped 4KB spaces. The LA commands are then translated into the
Interlaken control words and data words, which are sent on TX side to TCAM
through SerDes lanes.

There are two 4KiB spaces defined within the LAC global register memory map.
There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor"
version), and a subset at 0x1000-0x1FFF.  The former is a superset of the
latter, and includes certain registers that should not be accessible to
partitioned software.  Separate nodes are used for each region, with a phandle
linking the hypervisor node to the normal operating node.

PROPERTIES

  - compatible
	Usage: required
	Value type: <string>
	Definition: Must include "fsl,interlaken-lac". This represents only
		those LAC CCSR registers not protected in partitioned
		software. The version of the device is determined by the LAC
		IP Block Revision Register (IPBRR0) at offset 0x0BF8.

		Table of correspondences between IPBRR0 values and example
		chips:
			Value		Device
			-----------	-------
			0x02000100	T4240

		The Hypervisor node has a different compatible. It must include
		"fsl,interlaken-lac-hv". This node represents the protected
		LAC register space and is required except inside a partition
		where access to the hypervisor node is to be denied.

  - fsl,non-hv-node
	Usage: required in "fsl,interlaken-lac-hv"
	Value type: <phandle>
	Definition: Points to the non-protected LAC CCSR mapped register space
		node.

  - reg
	Usage: required
	Value type: <prop-encoded-array>
	Definition: A standard property. The first resource represents the
		Interlaken LAC configuration registers.

  - interrupts:

Annotation

Implementation Notes