Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
Extension
.yaml
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15273 bytes
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379
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G2L General PWM Timer (GPT)

maintainers:
  - Biju Das <biju.das.jz@bp.renesas.com>

description: |
  RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer
  (GPT32E). It supports the following functions
  * 32 bits x 8 channels.
  * Up-counting or down-counting (saw waves) or up/down-counting
    (triangle waves) for each counter.
  * Clock sources independently selectable for each channel.
  * Two I/O pins per channel.
  * Two output compare/input capture registers per channel.
  * For the two output compare/input capture registers of each channel,
    four registers are provided as buffer registers and are capable of
    operating as comparison registers when buffering is not in use.
  * In output compare operation, buffer switching can be at crests or
    troughs, enabling the generation of laterally asymmetric PWM waveforms.
  * Registers for setting up frame cycles in each channel (with capability
    for generating interrupts at overflow or underflow)
  * Generation of dead times in PWM operation.
  * Synchronous starting, stopping and clearing counters for arbitrary
    channels.
  * Starting, stopping, clearing and up/down counters in response to input
    level comparison.
  * Starting, clearing, stopping and up/down counters in response to a
    maximum of four external triggers.
  * Output pin disable function by dead time error and detected
    short-circuits between output pins.
  * A/D converter start triggers can be generated (GPT32E0 to GPT32E3)
  * Enables the noise filter for input capture and external trigger
    operation.

  The below pwm channels are supported.
    pwm0  - GPT32E0.GTIOC0A channel
    pwm1  - GPT32E0.GTIOC0B channel
    pwm2  - GPT32E1.GTIOC1A channel
    pwm3  - GPT32E1.GTIOC1B channel
    pwm4  - GPT32E2.GTIOC2A channel
    pwm5  - GPT32E2.GTIOC2B channel
    pwm6  - GPT32E3.GTIOC3A channel
    pwm7  - GPT32E3.GTIOC3B channel
    pwm8  - GPT32E4.GTIOC4A channel
    pwm9  - GPT32E4.GTIOC4B channel
    pwm10 - GPT32E5.GTIOC5A channel
    pwm11 - GPT32E5.GTIOC5B channel
    pwm12 - GPT32E6.GTIOC6A channel
    pwm13 - GPT32E6.GTIOC6B channel
    pwm14 - GPT32E7.GTIOC7A channel
    pwm15 - GPT32E7.GTIOC7B channel

properties:
  compatible:
    items:
      - enum:
          - renesas,r9a07g044-gpt  # RZ/G2{L,LC}
          - renesas,r9a07g054-gpt  # RZ/V2L
      - const: renesas,rzg2l-gpt

  reg:
    maxItems: 1

  '#pwm-cells':

Annotation

Implementation Notes