Documentation/devicetree/bindings/regulator/maxim,max77620-regulator.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/regulator/maxim,max77620-regulator.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/regulator/maxim,max77620-regulator.yaml- Extension
.yaml- Size
- 4210 bytes
- Lines
- 100
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/maxim,max77620-regulator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Regulator for MAX77620 Power management IC from Maxim Semiconductor.
maintainers:
- Svyatoslav Ryhel <clamor95@gmail.com>
description:
Device has multiple DCDC(sd[0-3]) and LDOs(ldo[0-8]). The input supply
of these regulators are defined under parent device node. Details of
regulator properties are defined as child node under sub-node "regulators"
which is child node of device node.
patternProperties:
"^in-(sd[0-3]|ldo(0-1|2|3-5|4-6|7-8))-supply$":
$ref: /schemas/types.yaml#/definitions/phandle
description: Input supply for DCDC or LDO
"^(sd[0-3]|ldo[0-8])$":
type: object
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
properties:
maxim,active-fps-source:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
FPS source for the GPIOs to get enabled/disabled when system is in
active state. Valid values are:
- MAX77620_FPS_SRC_0: FPS source is FPS0.
- MAX77620_FPS_SRC_1: FPS source is FPS1
- MAX77620_FPS_SRC_2: FPS source is FPS2
- MAX77620_FPS_SRC_NONE: GPIO is not controlled by FPS events and
it gets enabled/disabled by register access.
Absence of this property will leave the FPS configuration register
for that GPIO to default configuration.
maxim,active-fps-power-up-slot:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Sequencing event slot number on which the GPIO get enabled when
master FPS input event set to HIGH. This is applicable if FPS source
is selected as FPS0, FPS1 or FPS2.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
maxim,active-fps-power-down-slot:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Sequencing event slot number on which the GPIO get disabled when
master FPS input event set to LOW. This is applicable if FPS source
is selected as FPS0, FPS1 or FPS2.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
maxim,suspend-fps-source:
$ref: /schemas/types.yaml#/definitions/uint32
description:
This is same as property "maxim,active-fps-source" but value get
configured when system enters in to suspend state.
maxim,suspend-fps-power-up-slot:
$ref: /schemas/types.yaml#/definitions/uint32
description:
This is same as property "maxim,active-fps-power-up-slot" but this
value get configured into FPS configuration register when system
enters into suspend. This is applicable if suspend state FPS source
is selected as FPS0, FPS1 or FPS2.
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.