Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
Extension
.yaml
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11512 bytes
Lines
369
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx R5F processor subsystem

maintainers:
  - Ben Levinsky <ben.levinsky@amd.com>
  - Tanmay Shah <tanmay.shah@amd.com>

description: |
  The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
  real-time processing based on the Cortex-R5F processor core from ARM.
  The Cortex-R5F processor implements the Arm v7-R architecture and includes a
  floating-point unit that implements the Arm VFPv3 instruction set.

properties:
  compatible:
    enum:
      - xlnx,zynqmp-r5fss
      - xlnx,versal-r5fss
      - xlnx,versal-net-r52fss

  "#address-cells":
    const: 2

  "#size-cells":
    const: 2

  ranges:
    description: |
      Standard ranges definition providing address translations for
      local R5F TCM address spaces to bus addresses.

  xlnx,cluster-mode:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1, 2]
    default: 1
    description: |
      The RPU MPCore can operate in split mode (Dual-processor performance), Safety
      lock-step mode(Both RPU cores execute the same code in lock-step,
      clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while
      core 1 runs normally). The processor does not support dynamic configuration.
      Switching between modes is only permitted immediately after a processor reset.
      If set to  1 then lockstep mode and if 0 then split mode.
      If set to  2 then single CPU mode. When not defined, default will be lockstep mode.
      In summary,
      0: split mode
      1: lockstep mode (default)
      2: single cpu mode

  xlnx,tcm-mode:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [0, 1]
    description: |
      Configure RPU TCM
      0: split mode
      1: lockstep mode

patternProperties:
  "^r(.*)@[0-9a-f]+$":
    type: object
    additionalProperties: false
    description: |
      The RPU is located in the Low Power Domain of the Processor Subsystem.
      Each processor includes separate L1 instruction and data caches and
      tightly coupled memories (TCM). System memory is cacheable, but the TCM
      memory space is non-cacheable.

Annotation

Implementation Notes