Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/reset/intel,rcu-gw.yaml
Extension
.yaml
Size
1621 bytes
Lines
66
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: System Reset Controller on Intel Gateway SoCs

maintainers:
  - Dilip Kota <eswara.kota@linux.intel.com>

properties:
  compatible:
    enum:
      - intel,rcu-lgm
      - intel,rcu-xrx200

  reg:
    description: Reset controller registers.
    maxItems: 1

  intel,global-reset:
    description: Global reset register offset and bit offset.
    $ref: /schemas/types.yaml#/definitions/uint32-array
    items:
      - description: Register offset
      - description: Register bit offset
        minimum: 0
        maximum: 31

  "#reset-cells":
    minimum: 2
    maximum: 3
    description: |
      First cell is reset request register offset.
      Second cell is bit offset in reset request register.
      Third cell is bit offset in reset status register.
      For LGM SoC, reset cell count is 2 as bit offset in
      reset request and reset status registers is same. Whereas
      3 for legacy SoCs as bit offset differs.

required:
  - compatible
  - reg
  - intel,global-reset
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    rcu0: reset-controller@e0000000 {
        compatible = "intel,rcu-lgm";
        reg = <0xe0000000 0x20000>;
        intel,global-reset = <0x10 30>;
        #reset-cells = <2>;
    };

    pwm: pwm@e0d00000 {
        compatible = "intel,lgm-pwm";
        reg = <0xe0d00000 0x30>;
        clocks = <&cgu0 1>;
        #pwm-cells = <2>;
        resets = <&rcu0 0x30 21>;
    };

Annotation

Implementation Notes