Documentation/devicetree/bindings/riscv/cpus.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/riscv/cpus.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/riscv/cpus.yaml
Extension
.yaml
Size
6921 bytes
Lines
235
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0 OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/cpus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RISC-V CPUs

maintainers:
  - Paul Walmsley <paul.walmsley@sifive.com>
  - Palmer Dabbelt <palmer@sifive.com>
  - Conor Dooley <conor@kernel.org>

description: |
  This document uses some terminology common to the RISC-V community
  that is not widely used, the definitions of which are listed here:

  hart: A hardware execution context, which contains all the state
  mandated by the RISC-V ISA: a PC and some registers.  This
  terminology is designed to disambiguate software's view of execution
  contexts from any particular microarchitectural implementation
  strategy.  For example, an Intel laptop containing one socket with
  two cores, each of which has two hyperthreads, could be described as
  having four harts.

allOf:
  - $ref: /schemas/cpu.yaml#
  - $ref: extensions.yaml
  - if:
      not:
        properties:
          compatible:
            contains:
              enum:
                - thead,c906
                - thead,c910
                - thead,c920
    then:
      properties:
        thead,vlenb: false

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - amd,mbv32
              - amd,mbv64
              - andestech,ax45mp
              - canaan,k210
              - nuclei,ux900
              - sifive,bullet0
              - sifive,e5
              - sifive,e7
              - sifive,e71
              - sifive,p550
              - sifive,rocket0
              - sifive,s7
              - sifive,u5
              - sifive,u54
              - sifive,u7
              - sifive,u74
              - sifive,u74-mc
              - spacemit,x100
              - spacemit,x60
              - thead,c906
              - thead,c908
              - thead,c910
              - thead,c920
          - const: riscv

Annotation

Implementation Notes