Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
Extension
.yaml
Size
8135 bytes
Lines
358
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mobileye EyeQ SoC system controller

maintainers:
  - Grégory Clement <gregory.clement@bootlin.com>
  - Théo Lebrun <theo.lebrun@bootlin.com>
  - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>

description:
  OLB ("Other Logic Block") is a hardware block grouping smaller blocks. Clocks,
  resets, pinctrl are being handled from here. EyeQ5 and EyeQ6L host a single
  instance. EyeQ6H hosts seven instances.

properties:
  compatible:
    items:
      - enum:
          - mobileye,eyeq5-olb
          - mobileye,eyeq6l-olb
          - mobileye,eyeq6h-acc-olb
          - mobileye,eyeq6h-central-olb
          - mobileye,eyeq6h-east-olb
          - mobileye,eyeq6h-west-olb
          - mobileye,eyeq6h-south-olb
          - mobileye,eyeq6h-ddr0-olb
          - mobileye,eyeq6h-ddr1-olb
      - const: syscon

  reg:
    maxItems: 1

  '#reset-cells':
    description:
      First cell is domain and optional if compatible has a single reset domain.
      Second cell is reset index inside that domain.
    enum: [ 1, 2 ]

  '#clock-cells':
    const: 1

  clocks:
    maxItems: 1
    description:
      Input parent clock to all PLLs. Expected to be the main crystal.

  clock-names:
    const: ref

  '#phy-cells':
    const: 1

patternProperties:
  '-pins?$':
    type: object
    description: Pin muxing configuration.
    $ref: /schemas/pinctrl/pinmux-node.yaml#
    additionalProperties: false
    properties:
      pins: true
      function:
        enum: [gpio,
               # Bank A
               timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0,
               spi1, refclk0,
               # Bank B

Annotation

Implementation Notes