Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml- Extension
.yaml- Size
- 3333 bytes
- Lines
- 127
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/qcom/qcom,sa8255p-geni-se-qup.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GENI Serial Engine QUP Wrapper Controller
maintainers:
- Praveen Talari <quic_ptalari@quicinc.com>
description:
Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
is a programmable module for supporting a wide range of serial interfaces
like UART, SPI, I2C, I3C, etc. A single QUP module can provide up to 8 Serial
Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
Wrapper controller is modeled as a node with zero or more child nodes each
representing a serial engine.
properties:
compatible:
oneOf:
- const: qcom,sa8255p-geni-se-qup
- items:
- const: qcom,sa8797p-geni-se-qup
- const: qcom,sa8255p-geni-se-qup
reg:
description: QUP wrapper common register address and length.
maxItems: 1
"#address-cells":
const: 2
"#size-cells":
const: 2
ranges: true
iommus:
maxItems: 1
dma-coherent: true
patternProperties:
"spi@[0-9a-f]+$":
type: object
description: GENI serial engine based SPI controller. SPI in master mode
supports up to 50MHz, up to four chip selects, programmable
data path from 4 bits to 32 bits and numerous protocol
variants.
additionalProperties: true
properties:
compatible:
oneOf:
- const: qcom,sa8255p-geni-spi
- items:
- const: qcom,sa8797p-geni-spi
- const: qcom,sa8255p-geni-spi
"i2c@[0-9a-f]+$":
type: object
description: GENI serial engine based I2C controller.
additionalProperties: true
properties:
compatible:
oneOf:
- const: qcom,sa8255p-geni-i2c
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.