Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml- Extension
.yaml- Size
- 3001 bytes
- Lines
- 97
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/ti/k3-ringacc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments K3 NavigatorSS Ring Accelerator
maintainers:
- Santosh Shilimkar <ssantosh@kernel.org>
- Grygorii Strashko <grygorii.strashko@ti.com>
description: |
The Ring Accelerator (RA) is a machine which converts read/write accesses
from/to a constant address into corresponding read/write accesses from/to a
circular data structure in memory. The RA eliminates the need for each DMA
controller which needs to access ring elements from having to know the current
state of the ring (base address, current offset). The DMA controller
performs a read or write access to a specific address range (which maps to the
source interface on the RA) and the RA replaces the address for the transaction
with a new address which corresponds to the head or tail element of the ring
(head for reads, tail for writes).
The Ring Accelerator is a hardware module that is responsible for accelerating
management of the packet queues. The K3 SoCs can have more than one RA instances
allOf:
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
properties:
compatible:
items:
- const: ti,am654-navss-ringacc
reg:
minItems: 4
items:
- description: real time registers regions
- description: fifos registers regions
- description: proxy gcfg registers regions
- description: proxy target registers regions
- description: configuration registers region
reg-names:
minItems: 4
items:
- const: rt
- const: fifos
- const: proxy_gcfg
- const: proxy_target
- const: cfg
msi-parent: true
ti,num-rings:
$ref: /schemas/types.yaml#/definitions/uint32
description: Number of rings supported by RA
ti,sci-rm-range-gp-rings:
$ref: /schemas/types.yaml#/definitions/uint32
description: TI-SCI RM subtype for GP ring range
required:
- compatible
- reg
- reg-names
- msi-parent
- ti,num-rings
- ti,sci-rm-range-gp-rings
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.