Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml

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Linux kernel
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Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
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.yaml
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Support Tooling And Documentation
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Documentation
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Support Tooling And Documentation: configuration, schema, or hardware description
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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: |+
  TI Programmable Real-Time Unit and Industrial Communication Subsystem

maintainers:
  - Suman Anna <s-anna@ti.com>

description: |+
  The Programmable Real-Time Unit and Industrial Communication Subsystem
  (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
  Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
  cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
  instruction RAMs, some internal peripheral modules to facilitate industrial
  communication, and an interrupt controller.

  The programmable nature of the PRUs provide flexibility to implement custom
  peripheral interfaces, fast real-time responses, or specialized data handling.
  The common peripheral modules include the following,
    - an Ethernet MII_RT module with two MII ports
    - an MDIO port to control external Ethernet PHYs
    - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial
      Ethernet functions
    - an Enhanced Capture Module (eCAP)
    - an Industrial Ethernet Timer with 7/9 capture and 16 compare events
    - a 16550-compatible UART to support PROFIBUS
    - Enhanced GPIO with async capture and serial support

  A PRU-ICSS subsystem can have up to three shared data memories. A PRU core
  acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
  0x0, but also has access to a secondary Data RAM (primary to the other PRU
  core) at its address 0x2000. A shared Data RAM, if present, can be accessed
  by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are
  common to both the PRU cores. Each PRU core also has a private instruction
  RAM, and specific register spaces for Control and Debug functionalities.

  Various sub-modules within a PRU-ICSS subsystem are represented as individual
  nodes and are defined using a parent-child hierarchy depending on their
  integration within the IP and the SoC. These nodes are described in the
  following sections.

  PRU-ICSS Node
  ==============
  Each PRU-ICSS instance is represented as its own node with the individual PRU
  processor cores, the memories node, an INTC node and an MDIO node represented
  as child nodes within this PRUSS node. This node shall be a child of the
  corresponding interconnect bus nodes or target-module nodes.

  See ../../mfd/syscon.yaml for generic SysCon binding details.

properties:
  $nodename:
    pattern: "^(pruss|icssg)@[0-9a-f]+$"

  compatible:
    enum:
      - ti,am3356-pruss  # for AM335x SoC family
      - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
      - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1
      - ti,am5728-pruss  # for AM57xx SoC family
      - ti,am625-pruss   # for K3 AM62x SoC family
      - ti,am642-icssg   # for K3 AM64x SoC family
      - ti,am654-icssg   # for K3 AM65x SoC family
      - ti,j721e-icssg   # for K3 J721E SoC family
      - ti,k2g-pruss     # for 66AK2G SoC family

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