Documentation/devicetree/bindings/sound/renesas,fsi.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/sound/renesas,fsi.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/sound/renesas,fsi.yaml
Extension
.yaml
Size
4152 bytes
Lines
138
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/renesas,fsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas FIFO-buffered Serial Interface (FSI)

maintainers:
  - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>

properties:
  $nodename:
    pattern: "^sound@.*"

  compatible:
    oneOf:
      # for FSI2 SoC
      - items:
          - enum:
              - renesas,fsi2-sh73a0  # SH-Mobile AG5
              - renesas,fsi2-r8a7740 # R-Mobile A1
          - enum:
              - renesas,sh_fsi2
      # for Generic
      - items:
          - enum:
              - renesas,sh_fsi
              - renesas,sh_fsi2

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    items:
      - description: Main FSI module clock
      - description: |
          SPU bus/bridge clock. On R8A7740, this clock must be enabled to allow
          register access as the FSI block is connected behind the SPU bus.
      - description: CPG DIV6 functional clocks for FSI port A
      - description: CPG DIV6 functional clocks for FSI port B
      - description: FSI dividers for port A used for audio clock generation
      - description: FSI dividers for port B used for audio clock generation
      - description: External clock inputs for FSI port A provided by the board
      - description: External clock inputs for FSI port B provided by the board

  clock-names:
    minItems: 1
    maxItems: 8
    items:
      enum:
        - fck  # Main FSI module clock
        - spu  # optional SPU bus/bridge clock
        - icka # optional CPG DIV6 functional clocks for FSI port A
        - ickb # optional CPG DIV6 functional clocks for FSI port B
        - diva # optional FSI dividers for port A used for audio clock generation
        - divb # optional FSI dividers for port B used for audio clock generation
        - xcka # optional External clock inputs for FSI port A provided by the board
        - xckb # optional External clock inputs for FSI port B provided by the board

  power-domains:
    maxItems: 1

  '#sound-dai-cells':
    const: 1

Annotation

Implementation Notes