Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml- Extension
.yaml- Size
- 6304 bytes
- Lines
- 197
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/irq.hdt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom SPI controller
maintainers:
- Kamal Dasu <kdasu.kdev@gmail.com>
- Rafał Miłecki <rafal@milecki.pl>
description: |
The Broadcom SPI controller is a SPI master found on various SOCs, including
BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
of:
MSPI : SPI master controller can read and write to a SPI slave device
BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
for flash reads and be configured to do single, double, quad lane
io with 3-byte and 4-byte addressing support.
Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
MSPI master can be used without BSPI. BRCMSTB SoCs have an additional instance
of a MSPI master without the BSPI to use with non flash slave devices that
use SPI protocol.
allOf:
- $ref: spi-controller.yaml#
properties:
compatible:
oneOf:
- description: Second Instance of MSPI BRCMSTB SoCs
items:
- enum:
- brcm,spi-bcm7425-qspi
- brcm,spi-bcm7429-qspi
- brcm,spi-bcm7435-qspi
- brcm,spi-bcm7445-qspi
- brcm,spi-bcm7216-qspi
- brcm,spi-bcm7278-qspi
- const: brcm,spi-bcm-qspi
- const: brcm,spi-brcmstb-mspi
- description: Second Instance of MSPI BRCMSTB SoCs
items:
- enum:
- brcm,spi-brcmstb-qspi
- brcm,spi-brcmstb-mspi
- brcm,spi-nsp-qspi
- brcm,spi-ns2-qspi
- const: brcm,spi-bcm-qspi
reg:
minItems: 1
maxItems: 5
reg-names:
minItems: 1
items:
- const: mspi
- const: bspi
- enum: [ intr_regs, intr_status_reg, cs_reg ]
- enum: [ intr_regs, intr_status_reg, cs_reg ]
- enum: [ intr_regs, intr_status_reg, cs_reg ]
interrupts:
minItems: 1
maxItems: 7
interrupt-names:
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/irq.h`, `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.