Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml- Extension
.yaml- Size
- 3479 bytes
- Lines
- 153
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/microchip,mpfs-clock.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip FPGA {Q,}SPI Controllers
description:
SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
fabric IP cores they are based on
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
properties:
compatible:
oneOf:
- items:
- enum:
- microchip,mpfs-qspi
- microchip,pic64gx-qspi
- const: microchip,coreqspi-rtl-v2
- enum:
- microchip,coreqspi-rtl-v2 # FPGA QSPI
- microchip,corespi-rtl-v5 # FPGA CoreSPI
- microchip,mpfs-spi
- items:
- const: microchip,pic64gx-spi
- const: microchip,mpfs-spi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
microchip,apb-datawidth:
description: APB bus data width in bits.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16, 32]
default: 8
microchip,frame-size:
description: |
Number of bits per SPI frame, as configured in Libero.
In Motorola and TI modes, this corresponds directly
to the requested frame size. For NSC mode this is set
to 9 + the required data frame size.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 4
maximum: 32
default: 8
microchip,protocol-configuration:
description: CoreSPI protocol selection. Determines operating mode
$ref: /schemas/types.yaml#/definitions/string
enum:
- motorola
- ti
- nsc
default: motorola
microchip,motorola-mode:
Annotation
- Immediate include surface: `dt-bindings/clock/microchip,mpfs-clock.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.