Documentation/devicetree/bindings/timer/nvidia,tegra-timer.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/timer/nvidia,tegra-timer.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/timer/nvidia,tegra-timer.yaml
Extension
.yaml
Size
4830 bytes
Lines
150
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra timer

maintainers:
  - Stephen Warren <swarren@nvidia.com>

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: nvidia,tegra210-timer
    then:
      properties:
        interrupts:
          # Either a single combined interrupt or up to 14 individual interrupts
          minItems: 1
          maxItems: 14
          description: >
            A list of 14 interrupts; one per each timer channels 0 through 13

  - if:
      properties:
        compatible:
          oneOf:
            - items:
                - enum:
                    - nvidia,tegra114-timer
                    - nvidia,tegra124-timer
                    - nvidia,tegra132-timer
                - const: nvidia,tegra30-timer
            - items:
                - const: nvidia,tegra30-timer
                - const: nvidia,tegra20-timer
    then:
      properties:
        interrupts:
          # Either a single combined interrupt or up to 6 individual interrupts
          minItems: 1
          maxItems: 6
          description: >
            A list of 6 interrupts; one per each of timer channels 1 through 5,
            and one for the shared interrupt for the remaining channels.

  - if:
      properties:
        compatible:
          const: nvidia,tegra20-timer
    then:
      properties:
        interrupts:
          # Either a single combined interrupt or up to 4 individual interrupts
          minItems: 1
          maxItems: 4
          description: |
            A list of 4 interrupts; one per timer channel.

properties:
  compatible:
    oneOf:
      - const: nvidia,tegra210-timer
        description: >
          The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
          timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
          from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock

Annotation

Implementation Notes