Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml

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Linux kernel
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Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
Extension
.yaml
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12615 bytes
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321
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)

maintainers:
  - Biju Das <biju.das.jz@bp.renesas.com>

description: |
  This hardware block consists of eight 16-bit timer channels and one
  32-bit timer channel. It supports the following specifications:
    - Pulse input/output: 28 lines max
    - Pulse input 3 lines
    - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
      for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
      (when LWA = 1))
    - Operating frequency Up to 100 MHz
    - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
        - Waveform output on compare match
        - Input capture function (noise filter setting available)
        - Counter-clearing operation
        - Simultaneous writing to multiple timer counters (TCNT)
          (excluding MTU8)
        - Simultaneous clearing on compare match or input capture
          (excluding MTU8)
        - Simultaneous input and output to registers in synchronization with
          counter operations (excluding MTU8)
        - Up to 12-phase PWM output in combination with synchronous operation
          (excluding MTU8)
    - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
        - Buffer operation specifiable
    - [MTU1, MTU2]
        - Phase counting mode can be specified independently
        - 32-bit phase counting mode can be specified for interlocked operation
          of MTU1 and MTU2 (when TMDR3.LWA = 1)
        - Cascade connection operation available
    - [MTU3, MTU4, MTU6, and MTU7]
        - Through interlocked operation of MTU3/4 and MTU6/7, the positive and
          negative signals in six phases (12 phases in total) can be output in
          complementary PWM and reset-synchronized PWM operation
        - In complementary PWM mode, values can be transferred from buffer
          registers to temporary registers at crests and troughs of the timer-
          counter values or when the buffer registers (TGRD registers in MTU4
          and MTU7) are written to
        - Double-buffering selectable in complementary PWM mode
    - [MTU3 and MTU4]
        - Through interlocking with MTU0, a mode for driving AC synchronous
          motors (brushless DC motors) by using complementary PWM output and
          reset-synchronized PWM output is settable and allows the selection
          of two types of waveform output (chopping or level)
    - [MTU5]
        - Capable of operation as a dead-time compensation counter
    - [MTU0/MTU5, MTU1, MTU2, and MTU8]
        - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
          through interlocked operation with MTU0/MTU5 and MTU8
    - Interrupt-skipping function
        - In complementary PWM mode, interrupts on crests and troughs of counter
          values and triggers to start conversion by the A/D converter can be
          skipped
    - Interrupt sources: 43 sources.
    - Buffer operation:
        - Automatic transfer of register data (transfer from the buffer
          register to the timer register).
    - Trigger generation
        - A/D converter start triggers can be generated
        - A/D converter start request delaying function enables A/D converter
          to be started with any desired timing and to be synchronized with

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Implementation Notes