Documentation/devicetree/bindings/timer/snps,archs-gfrc.yaml

File Facts

System

Linux kernel

Corpus path

Documentation/devicetree/bindings/timer/snps,archs-gfrc.yaml

Extension

.yaml

Size

560 bytes

Lines

31

Domain

Support Tooling And Documentation

Bucket

Documentation

Inferred role

Support Tooling And Documentation: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

• Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/snps,archs-gfrc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs

maintainers:
  - Vineet Gupta <vgupta@synopsys.com>

properties:
  compatible:
    const: snps,archs-gfrc

  clocks:
    maxItems: 1

required:
  - compatible
  - clocks

additionalProperties: false

examples:
  - |
    timer {
        compatible = "snps,archs-gfrc";
        clocks = <&core_clk>;
    };

Annotation

• Atlas domain: Support Tooling And Documentation / Documentation.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.