Documentation/driver-api/cxl/devices/device-types.rst

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=====================
Devices and Protocols
=====================

The type of CXL device (Memory, Accelerator, etc) dictates many configuration steps. This section
covers some basic background on device types and on-device resources used by the platform and OS
which impact configuration.

Protocols
=========

There are three core protocols to CXL.  For the purpose of this documentation,
we will only discuss very high level definitions as the specific hardware
details are largely abstracted away from Linux.  See the CXL specification
for more details.

CXL.io
------
The basic interaction protocol, similar to PCIe configuration mechanisms.
Typically used for initialization, configuration, and I/O access for anything
other than memory (CXL.mem) or cache (CXL.cache) operations.

The Linux CXL driver exposes access to .io functionality via the various sysfs
interfaces and /dev/cxl/ devices (which exposes direct access to device
mailboxes).

CXL.cache
---------
The mechanism by which a device may coherently access and cache host memory.

Largely transparent to Linux once configured.

CXL.mem
---------
The mechanism by which the CPU may coherently access and cache device memory.

Largely transparent to Linux once configured.


Device Types
============

Type-1
------

A Type-1 CXL device:

* Supports cxl.io and cxl.cache protocols
* Implements a fully coherent cache
* Allows Device-to-Host coherence and Host-to-Device snoops.
* Does NOT have host-managed device memory (HDM)

Typical examples of type-1 devices is a Smart NIC - which may want to
directly operate on host-memory (DMA) to store incoming packets. These
devices largely rely on CPU-attached memory.

Type-2
------

A Type-2 CXL Device:

* Supports cxl.io, cxl.cache, and cxl.mem protocols
* Optionally implements coherent cache and Host-Managed Device Memory
* Is typically an accelerator device with high bandwidth memory.

The primary difference between a type-1 and type-2 device is the presence
of host-managed device memory, which allows the device to operate on a
local memory bank - while the CPU still has coherent DMA to the same memory.

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Implementation Notes