Documentation/driver-api/cxl/maturity-map.rst

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Documentation/driver-api/cxl/maturity-map.rst
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.. SPDX-License-Identifier: GPL-2.0
.. include:: <isonum.txt>

===========================================
Compute Express Link Subsystem Maturity Map
===========================================

The Linux CXL subsystem tracks the dynamic `CXL specification
<https://computeexpresslink.org/cxl-specification-landing-page>`_ that
continues to respond to new use cases with new features, capability
updates and fixes. At any given point some aspects of the subsystem are
more mature than others. While the periodic pull requests summarize the
`work being incorporated each merge window
<https://lore.kernel.org/linux-cxl/?q=s%3APULL+s%3ACXL+tc%3Atorvalds+NOT+s%3ARe>`_,
those do not always convey progress relative to a starting point and a
future end goal.

What follows is a coarse breakdown of the subsystem's major
responsibilities along with a maturity score. The expectation is that
the change-history of this document provides an overview summary of the
subsystem maturation over time.

The maturity scores are:

- [3] Mature: Work in this area is complete and no changes on the horizon.
  Note that this score can regress from one kernel release to the next
  based on new test results or end user reports.

- [2] Stabilizing: Major functionality operational, common cases are
  mature, but known corner cases are still a work in progress.

- [1] Initial: Capability that has exited the Proof of Concept phase, but
  may still have significant gaps to close and fixes to apply as real
  world testing occurs.

- [0] Known gap: Feature is on a medium to long term horizon to
  implement.  If the specification has a feature that does not even have
  a '0' score in this document, there is a good chance that no one in
  the linux-cxl@vger.kernel.org community has started to look at it.

- X: Out of scope for kernel enabling, or kernel enabling not required

Feature and Capabilities
========================

Enumeration / Provisioning
--------------------------
All of the fundamental enumeration an object model of the subsystem is
in place, but there are several corner cases that are pending closure.


* [2] CXL Window Enumeration

  * [2] :ref:`Extended-linear memory-side cache <extended-linear>`
  * [0] Low Memory-hole
  * [X] Hetero-interleave

* [2] Switch Enumeration

  * [0] CXL register enumeration link-up dependency

* [2] HDM Decoder Configuration

  * [0] Decoder target and granularity constraints

* [2] Performance enumeration

  * [3] Endpoint CDAT
  * [3] Switch CDAT
  * [1] CDAT to Core-mm integration

Annotation

Implementation Notes