Documentation/hwmon/sbtsi_temp.rst

Source file repositories/reference/linux-study-clean/Documentation/hwmon/sbtsi_temp.rst

File Facts

System: Linux kernel
Corpus path: Documentation/hwmon/sbtsi_temp.rst
Extension: .rst
Size: 1558 bytes
Lines: 43
Domain: Support Tooling And Documentation
Bucket: Documentation
Inferred role: Support Tooling And Documentation: documentation
Status: atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

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Annotated Snippet

.. SPDX-License-Identifier: GPL-2.0-or-later

Kernel driver sbtsi_temp
========================

Supported hardware:

  * Sideband interface (SBI) Temperature Sensor Interface (SB-TSI)
    compliant AMD SoC temperature device.

    Prefix: 'sbtsi_temp'

    Addresses scanned: This driver doesn't support address scanning.

    To instantiate this driver on an AMD CPU with SB-TSI
    support, the i2c bus number would be the bus connected from the board
    management controller (BMC) to the CPU. The i2c address is specified in
    Section 6.3.1 of the SoC register reference: The SB-TSI address is normally
    98h for socket 0 and 90h for socket 1, but it could vary based on hardware
    address select pins.

    Datasheet: The SB-TSI interface and protocol is available as part of
               the open source SoC register reference at:

	       https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf

               The Advanced Platform Management Link (APML) Specification is
               available at:

	       http://developer.amd.com/wordpress/media/2012/10/41918.pdf

Author: Kun Yi <kunyi@google.com>

Description
-----------

The SBI temperature sensor interface (SB-TSI) is an emulation of the software
and physical interface of a typical 8-pin remote temperature sensor (RTS) on
AMD SoCs. It implements one temperature sensor with readings and limit
registers encode the temperature in increments of 0.125 from 0 to 255.875.
Limits can be set through the writable thresholds, and if reached will trigger
corresponding alert signals.

Annotation

Atlas domain: Support Tooling And Documentation / Documentation.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.